This invention relates to improvements in micro-machining, perhaps in a particular example to improvements in manufacturing motion sensors.
It is known to produce micro-mechanical sensors using micro-machining techniques. In particular, GB 2 276 976 shows a particular method for the production of such a sensor wherein a silicon wafer has cavities formed into its surface. Next a second wafer is bonded to the surface of the first wafer and the second wafer etched in a manner to release portions of the second wafer which are above the cavities in the first wafer. Thus, suspended resonating portions are formed which exist above the cavities in the first wafer.
Further, WO 95/08775 shows a structure wherein a layer of silicon is formed onto a substrate. The silicon is etched in a manner to form suspended resonator portions above cavities in the silicon.
One such micro-mechanical sensor is the vibratory gyroscope which measures the rate of turn and has applications in the fields of vehicle control, smart munitions, robotics, virtual reality, leisure and medicine as well as other fields.
According to a first aspect of the invention there is provided a method of fabricating a micro-mechanical sensor comprising taking a first wafer with an insulating layer formed thereon and with a second insulating layer bonded to the insulating layer and
a) patterning and subsequently etching one of either the first or second wafers such that channels are created in said one wafer (the etched wafer) terminating adjacent to the insulating layer; and
b) etching the insulating layer to remove portions of the insulating layer adjacent the etched wafer such that those portions of the etched wafer below a predetermined size, suspended portions, become substantially freely suspended above the other wafer.
Preferably the method is used to fabricate micro mechanical sensors or micro mechanical actuators.
Such a method leaves portions of the etched wafer which are above the predetermined size attached to said other wafer through the insulating layer. Thus, the micro-mechanical sensor so formed comprises both suspended portions and also portions anchored to the other wafer by the insulating layer.
During an etch, etchants will generally etch any free surfaces of a target material which they contact. Therefore, if a volume of target material is exposed to an etchant it will be etched from each of the sides which the etchant contacts. The length of time it takes the etchant to completely remove the target material will depend upon the shortest distance from an edge portion of the volume to the centre of the volume. Thus a long thin shape will be remove before a square shape of equal volume. Thus, the predetermined size above which suspended portions become separated from the other wafer depends upon the dimensions of the volume of the insulating layer being etched.
Step b) of the process may be performed in a single pattern and etch step or may be as a series of pattern and etch steps.
The insulating layer may be thought of as a sacrificial layer and as an anchoring layer. However, the skilled person will appreciate that the insulating layer has insulating properties which may be utilised.
The method according to the first aspect of the invention is simpler to use that prior art methods. The resulting reduction in process complexity is an advantage over both sacrificial surface micro-machining (SSM) and traditional bulk micro-machining (TBM) technologies.
Further advantages of the method are that structures formed in the etched wafer can be made with a greater depth than in prior art methods using surface micromaching (SSM) wherein layers are deposited or other types of Silicon On Insulator processing. Typical depth limits for a deposited layer are between 10 xcexcm-20 xcexcm. It would not have been possible to reliably deposit material to the depth achieved by the present method. For instance providing material by deposition has the problem that the uniformity of the material is hard to control with errors of 5% across a wafer being typical. Further, the process provides a buried insulating layer.
Further, as the thickness of a deposited layer increases the internal stresses within the layer of deposited material increase and can eventually lead to the deposited layer delaminating itself from the material upon which the material was deposited. The present method may be used to fabricate structures having a depth of up to substantially 2 mm. Possibly this may be increased to 2.5 mm, 3 mm, 3.5 mm or 4 mm.
The skilled person will appreciate that it is beneficial to have deeper structures since they will be stiffer and will therefore have better mechanical properties. Further it is advantageous to have the structures fabricated from single crystal material rather than from deposited material since this also leads to many beneficial properties within the formed structures.
The skilled person will realise that wafers can be purchased which comply with the starting steps of the method; that is a sandwich structure of two wafers with an insulating layer provided between them. Therefore, the starting point in the process may be the commercially available sandwich structure. The method may however, include the steps of fabricating an insulating layer onto a first wafer and subsequently bonding the second wafer to the insulating layer.
Further it will also be appreciated that the cost of a wafer with silicon and insulating layers provided on the surface is higher than the cost of a wafer without the extra layers provided. The combined advantages of the invention may more than offset the higher cost of the wafer with the extra layers compared to a standard wafer.
The skilled person will appreciate that the gap between the suspended portions defined from said one layer and said other wafer is defined by the thickness of the insulating layer and therefore by controlling the thickness of the insulating layer between the first and second wafers this gap may be controlled. The thickness of the insulating layer may be substantially in the range 10 nm to 20 xcexcm. More preferably the insulating layer has a thickness substantially in the range 100 nm to 10 xcexcm. In the most preferred embodiments the thickness lies substantially in the range 1 xcexcm to 5 xcexcm. In particular, layer thickness of substantially 1.5 xcexcm and 3 xcexcm may be suitable.
Preferably the first wafer is a mechanical wafer which undergoes subsequent processing to have the structure formed therein. An advantage of forming the insulating layer on the mechanical wafer is that a cleaner interface is formed for subsequent processing (for example etching).
A further advantage of providing the first wafer as the mechanical wafer is that the devices subsequently formed from the mechanical wafer are formed from the single crystal structure of the wafer. As previously discussed this has advantages, namely it is likely that devices formed will have a higher reliability and that resonant devices formed will have a higher quality factor when compared to structures formed in polycrystalline materials of prior art methods. However, the single crystal of the wafer often shows anisotropic properties and considerations may arise which need to be considered in the design stage to account for the anisotropic nature. The anisotropic properties may depend on factors including crystal orientation of the material and the accuracy of any cut of the crystal.
Preferably the second wafer is a substrate or handle wafer which is provided as a support for the micro-mechanical sensor.
Of course, the first wafer may be a substrate or handle wafer and the second wafer may be a mechanical wafer which undergoes subsequent processing (for example etching). Such a structure is equally possible but the interface between the mechanical wafer and the insulating layer tends to be of poorer quality since this is where bonding occurs.
One company capable of providing a sandwich structure capable of being used for the start of the method is BCO Technologies (NI) Ltd., Belfast, BT11 8BU.
The method may comprise an additional step of polishing the wafer to be etched (which may be either the first or second wafer) to the desired thickness. This polishing may be performed as part of bonding the second wafer to the insulating layer or as an additional step before step a) of the method is performed. This has the advantage that the micro-mechanical sensor so formed by the method can be tailored to the correct thickness. The polishing may be performed by mechanical means (for instance grinding), or may be by chemical means (for instance etching) or may be by a combination of mechanical and chemical means (chemical-mechanical means).
An advantage of the present method is that the wafer being polished is supported over its entire area by a combination of the other wafer and the insulating layer. In some prior art methods a wafer which was not supported over its entire area was polished which in some instances led to buckling of the wafer over the unsupported areas.
During step a) of the method wet chemical etchants may be used to etch the channels into the etched wafer and isotropic or anisotropic profiles may be provided.
Alternatively, or additionally, dry etching may be used. Such etching is advantageous because it increases the aspect ratio of depth to width which can be achieved by using wet etching. Also, the minimum feature size may be reduced and density of features may be increased using dry etching. In particular, a deep dry etcher such as an advanced silicon etch (ASE) system produced by Surface Technology Systems using a fluorine based inductively coupled plasma may be used.
Further, the packing density may be increased by the use of dry etching over that for wet processes associated with TBM which may reduce unit costs.
Yet another advantage of using dry etching arises from the following. Since the aspect ratio of the etch is increased the depth of the micro-mechanical sensor may be increased over prior art structures. Therefore, the mass of portions below the predetermined cross sectional area which are substantially freed during step b) (the suspended portions) of the method may be increased over the masses of comparable structures formed by SSM techniques. An advantage of having higher masses for the suspended structures is that the sensor sensitivity is increased. The mass of the suspended structure may be increased by an order of magnitude when compared to structures provided the traditional SSM techniques.
Preferably the mask for the etch of step a) is optimised so that the areas to be etched have substantially equal cross sectional areas and pattern density. This may be important should a deep dry etcher be used; the rate of etch for such a system is dependent on cross sectional area and pattern density and therefore should regions having different cross sectional areas or pattern densities be used they will etch at different rates.
Preferably the method includes providing suspensory ligaments between the suspended portions and the remainder of the etched wafer. These suspensory ligaments have the advantage that when the suspended portions are released from the other wafer (by the removal of the insulating layer) they are maintained in situ by the suspensory ligament. The suspensory ligaments may comprise portions of the etched wafer which remain after the etching processes.
A further advantage of a high aspect ratio etching process for step a) of the method is that the stiffness of the suspensory ligament is increased in the vertical direction when compared to suspensory ligaments which would have been fabricated from prior art methods (there is now a greater height to width ratio when compared to prior art structures which had a much lower depth).
The higher stiffness for the suspensory ligament is advantageous in that for resonant sensors parasitic modes of oscillation may be reduced. That is if the sensor is stiffened in a z-axis direction of a Cartesian co-ordinate system cross talk to the x and y axis is reduced. Further, the higher stiffness may be advantageous in that the likelihood of the suspended portions sticking to the un-etched wafer are reduced.
The etchant used in step b) of the method may be a wet chemical etchant. Alternatively, or additionally, the etchant to be used in step b) may be a dry etchant such as a vapour or gaseous etchant or may be plasma or ion beam.
In some processes it may be desirable to use a vapour etchant for step b) of the method. When using wet etchants stiction problems may arise due to surface tension effects as the etchant dries causing the suspended portions to stick to the other wafer or to portions of the etched wafer above the predetermined cross sectional area. Residues may form as a result of the vapour etch phase (for example with HF gas), which may possibly be due to dopants (for example phosphorous) in the insulating layer.
The method may comprise the step of cleaning the etched areas of the insulating layer with another gaseous or vapour phase agent, for example steam to remove the residues. Stiction problems associated with having wet surfaces between the suspended portions and the remainder of the first and second wafers are therefore removed or lessened (that is the stiction problems associated with using a wet etchant).
The structure may be held at a temperature of greater than substantially the boiling point of the vapour being used whilst the cleaning is being performed. In the preferred embodiment the structure is held significantly above substantially 100xc2x0 C. whilst cleaning is being performed. Possibly the structure is held at approximately 150xc2x0 C. When as in the preferred embodiment the vapour used is steam this ensures that the steam does not condense wetting the surfaces and potentially causing stiction problems. In some embodiments steam used may be further superheated, possibly to approximately 200xc2x0 C. or more.
It may be possible to refill (with a refill material) some of the channels created in the etched wafer prior to the performing of step b). This is advantageous in that it allows small features below the predetermined cross sectional area to be laterally anchored to features above the predetermined cross sectional area such that they are held in place once the sacrificial insulating layer between the mechanical and handle wafers is partially removed.
Should the channels be refilled, surface layers (for example metallisation) may be deposited upon, or laid across, the refilled channel. This has the advantage that the metallisation could reach electrically isolated parts which would otherwise be mechanically and electrically isolated by the channel.
The material used to refill the channels may be a nitride which is advantageous in that it may be deposited as a low stress layer on the surrounding wafer. Preferably the nitride is provided by PECVD. The nitride may be silicon nitride.
Of course, the skilled person will appreciate that the material used to refill the channel could be a material other than a nitride. Indeed, a polymer such as a polyimide, or may be a photoresist, would be a suitable refill material. A polyimide or photoresist is advantageous in situations where it is required to form electrical pathways over a channel. Once the electrical pathway has been created the method may comprise removing the refill material to re-create the channel. The polyimide may be PIQ(trademark).
Alternatively, or additionally the channels may be refilled with polysilicon and/or an oxide of the material from which the wafer is fabricated (hereinafter referred to as an oxide) either of which may be deposited by processes such as TEOS or PECVD.
The refill material may contain voids. The skilled person will appreciate that the quality of the refill material does not necessarily have to be high.
Buried or covered contacts may be provided in the insulating layer as it is formed onto the surface of the first wafer. The contacts buried in the insulating layer may be formed from at least any one of the following materials: polysilicon, silicides. Of course, the skilled person will realise that any other conductor could be used if it is capable of withstanding the temperatures involved in the bonding process.
The skilled person will appreciate that electrical connections may necessarily be made which bridge suspended portions. In such circumstances provision needs to be made for the connections before or after step b) of the process is performed. Such connections could possibly be made by our co-pending application entitled xe2x80x9cImprovements relating to micro-machiningxe2x80x9d and filed on the same day as this application.
Preferably the first and second wafers are provided from a semi-conductor. Most preferably, the first and second wafers are provided from silicon.
Preferably the method is fully compatible with CMOS processing. The method may comprise providing integrated circuits in association with the sensor such that a sensor is provided in a single package with the necessary processing electronics.
The insulating layer between the first and second wafers may comprise more than one material. The different materials may be laid down in layers. In one embodiment there are provided two materials in three layers. In another embodiment there are provided three materials in four layers.
Should different materials be used to form the insulating layer, each, or some of, the materials may have a different etch rate.
The materials forming the insulating layer may be an oxide. Further, the materials forming the insulating layer may be doped or undoped oxides. Preferably, there is provided at least one layer of undoped oxide and at least one layer of doped oxide. In the most preferred embodiment there are provided two layers of undoped oxide sandwiching a layer of doped oxide. In the most preferred embodiment there may or may not be provided a layer of nitride in the insulating layer.
In other embodiments the insulating layer may be formed from at least one layer of nitride. Such a nitride layer may be doped or undoped. There may be provided at least one doped layer of nitride and at least one layer of undoped nitride. Indeed, there may be provided two layers of doped nitride sandwiching a layer of undoped nitride.
In yet another embodiment the insulating layer may be polymer based, possibly a polyimide. There may be provided an insulating layer which is a sandwich structure of any of the following: conducting layers, insulating layers, semiconducting layers, polymer layers.
Providing the insulating layer in a plurality of layers is advantageous because it can aid the release of the suspended portions from the remaining portions. As the skilled person will appreciate a doped oxide will etch faster than an undoped oxide. Therefore by providing a layer of doped oxide between two layers of undoped oxide the middle, doped oxide, layer will etch faster. By controlling the time period of the etch of the insulating layer it is possible to stop the etch once all of the middle doped oxide layer has been removed but with portions of the undoped oxide remaining. The portions of undoped oxide will tend to prevent stiction between the suspended portions and the remaining portions. That is the portions of undoped oxide remaining may help to prevent stick down (due to surface tension effects) after the freeing process. The remaining portions of undoped oxide may be thought of as a series of bumps which reduce the contact surface area.
Further, it is advantageous to provide the insulating layer by a deposition process (which may be PECVD) since deposited layer will grow faster than thermally grown layers. Also, the PECVD process can be tailored so that either compressive of tensile stresses are left in the deposited layer. Therefore, should a plurality of layers be deposited the method may include the steps of depositing the insulating layer such that a compressive layer is followed by a tensile layer (or visa versa) such that there is substantially zero stress in the combined layers. Of course, as discussed hereinbefore, there may be more than two layers deposited.
By choosing the material of the layers within the insulating layer it may be possible to eliminate strain between the first and second wafer; that is for the strain imparted on the various layers to cancel out so that there is zero net imparted to the wafers.
The portions of undoped oxide remaining may be at a centre region of the suspended portions or may be between channels formed through the suspended portions (which may be thought of as access holes).
A further advantage of having the doped layer bounded by the undoped layers is that the undoped layers may act as a barrier to the prevent the dopants migrating into the wafers during bonding of the second wafer to the insulating layer should the undoped layer have a great enough thickness.
Nitride and oxide layers typically have a lower stiction coefficient than silicon layers and therefore the inclusion of such a layer can also allow the suspended portions to be released more easily. Further, nitride layers are insulators and will not be etched by the same wet etchant used to remove any oxide layer which has been provided if the etchant is selective. Therefore, should a nitride layer be provided it will remain in place during any etch of an oxide layer provided within the insulating layer. Thus, once substantially freed, the suspended portions of the etched wafer will be electrically insulated from the unetched wafer should the suspended portion ever contact the unetched wafer due to the nitride layer even though other layers of the insulating layer have been substantially removed.
Preferably any layers provided within the insulating layer are formed using Plasma Enhanced Chemical Vapour Deposition (PECVD). As discussed hereinbefore such layers etch faster than layers provided by other techniques. Also, because PECVD processes occur at relatively low temperatures when compared to other processes there are likely to be lower stresses within the insulating layer. In particular, the insulating layer may be provided by the use of PECVD followed by an anneal step. The anneal step is advantageous because it may improve the yield of the method. Indeed in some embodiments a rapid thermal anneal may be used wherein the insulating layer is exposed to a high temperature for a short period of time.
An advantage of using deposited layers (as opposed to thermally grown layers) is that the deposited layers etch faster, possibly two orders of magnitude quicker than thermally grown layers.
Further, it may be preferred to incorporate dopants into the deposited layers since these will cause the deposited layers to reflow at lower temperatures and may increase etch rates further still. Suitable dopants for incorporation into the deposited layers may include any from the following list (but is not limited to this list): Phosphorous, Boron, Antimony, Arsenic, Germanium.
Using the annealing process it is possible to bond the second wafer to an oxide deposited fabrication of the insulating layer which has been deposited in a LPCVD (Low Temperature Oxide) process. Deposited layers tend to etch faster than thermally grown layers and it may therefore be preferred to provide the insulating layer by a deposition process (such as PECVD or LPCVD) rather than by thermal growth.
The skilled person will appreciate that the thickness of the wafer etched in step b). Will define the thickness of elements of the sensor formed by the method. The thickness of the etched wafer, at the start of step b), may lie substantially in the range 1 xcexcm to 1 mm. More preferably the thickness of the etched wafer at the start of process d) lies substantially in the range 10 xcexcm to 200 xcexcm.
The method may produce elements of the sensor which are thinner than the surrounding wafer by locally thinning the wafer, for example using an etching process.
According to a second aspect of the invention there is provided a micro mechanical device fabricated according to the method of the first aspect of the invention.
The sensor may any one of the following: gyroscope, accelerometer, resonating beam, or any other resonant or micro-mechanical sensor. It may also be possible to fabricate an actuator or a combination of a sensor and actuator (for example a micro robot capable of measuring and interacting with its environment). The device may incorporate a resonator.
According to a third aspect of the invention there is provided a method of fabricating a micro-mechanical sensor comprising the following steps:
a) forming an insulating layer onto a top most surface of a first wafer;
b) etching portions of the insulating layer;
c) bonding a second wafer to the insulating layer; and
d) etching a bottom most surface of one of the wafers, the etched wafer, adjacent the etched portions of the insulating layer such that portions of the etched wafer become substantially free (suspended portions) from the remainder of the first and second wafers.
No etching step to remove portions of the insulating layer after the second wafer has been bonded are required in this method and therefore problems associated with stiction of the suspended portions to the remainder of the wafers are avoided.
Preferably it is the first wafer which has its bottom most surface etched. This is advantageous because of the cleaner interface between the first wafer and the insulating layer (because the insulating layer was formed upon the first wafer).
The method may comprise a step before step a) wherein marker channels, having a top end portion near to a top surface of the wafer and a bottom end portion distal from the top end portion, preferably substantially perpendicular to the surface of the wafer, are etched into the first wafer. These marker channels may have a depth substantially equal to the depth of the wafer through which they have been fabricated. These marker channels are advantageous as they can act as alignment markers for the remainder of the process and may align features from the back of the wafer to the front of the wafer. Indeed, the features so aligned may be buried on the back of the wafer.
In addition to fabricating marker channels before step a) other portions of the wafer may be removed by patterning and etching. This may allow portions of the wafer to be thinned (that is have their depth reduced) when followed by etching from the front of the wafer. One possible use of such a thinning would be to allow the sensitive axis of the device being fabricated to be out of the plane of the wafer.
As discussed hereinbefore if a portion has a large stiffness in a first direction along the z axis of a Cartesian co-ordinate system cross talk to the x and y axis will be reduced. Therefore, by reducing the stiffness in the z axis the sensitivity of the device can be tailored in the x and y axial directions. The method may comprise tailoring the sensitivity as desired.
Preferably the insulating layer formed during step a) of the process fills any channels formed in the first wafer.
The method may comprise another step, between steps c) and d), wherein the first wafer is polished to the desired thickness. The polishing may be mechanical (perhaps using a diamond paste), or may be chemical, or may be a combination of mechanical and chemical etching may be chemical-mechanical. The skilled person will appreciate that should the first wafer be polished it is the bottom most surface, that is the surface without the insulating layer, which is polished.
In the preferred embodiment polishing of the wafer removes the first wafer such that the bottom end portions of the marker channels are revealed. This is advantageous because the marker channels are now visible at the bottom most surface of the wafer. The skilled person will appreciate that after step c) of the method the top most surface of the first wafer is covered by both the insulating layer and the second wafer attached to the insulating layer and that therefore, the channels (acting as alignment markers) etched into the first wafer are covered. By forming the channels to a depth equal to or greater than the depth of the sensor it is possible to make the channels visible once more during the polishing process such that the channels can be used to align the etching process of step d).
As with the method of the first aspect of the invention Silicon On Insulator (SOI) wafers could be obtained pre-fabricated and therefore steps a) and b) of the process could be pre-formed.
The method may comprise a further step between steps b) and c) wherein the portions of the insulating layer which have been etched are refilled with a filler material. The filler material may be a material which has an etch rate substantially equal to that of the wafer material during step d) of the method. The filler material may be substantially the same material as the wafer (for example if the wafer is silicon the filler material may be polysilicon). Alternatively, the filler material may be a conductive material, for example a silicide, or TiW. Preferably the etching of step d) is arranged to be coincident with the refilled etched portions in the insulating layer.
It is known that during certain high aspect ratio etches through a wafer in an SOI structure that when an etch over runs the wafer through which the etch is passing may be damaged (for example by doming) as the etch meets the insulating layer. This occurs as the etch reaches the insulating layer. The low etch rate combined with charging effects means that ions at the junction of the materials may cause doming. If the filler material is of the same material as the wafer it will be etched as if part of the main wafer and so little or no doming may occur. Also, if the filler material is a conductor the charge on the ions can be carried away by the conductor thus also reducing the problem by reducing charging effects which accelerate the ions toward side walls. Therefore, an advantage of having a portion of the insulating layer removed and refilled is that if an etch, as described herein, is allowed to over run it may simply etch the refill material as opposed to damaging the wafer.
According to a fourth aspect of the invention there is provided a method of forming an alignment marker comprising the following steps:
a) forming channels into a top-most surface of a wafer substantially perpendicular to the surface of the wafer, the channels having a top-most end portion adjacent the top-most surface of the wafer and a bottom end most portion distal the top-most end portion;
b) providing a layer onto the surface of the wafer which fills the channels;
c) polishing the wafer from a rear-most surface at least until the bottom end portion of the channel is exposed through the rear-most surface of the wafer.
Polishing the rear-most surface of the wafer may occur until the channel is exposed through the rear-most surface of the wafer. Alternatively polishing may occur until the channel is visible using infra-red imaging through the rear-most surface of the wafer.
This method is advantageous in that initial processing can be performed on the top-most surface of the wafer and subsequent processing can be carried out on the rear-most surface of the wafer with the processing steps on the opposite sides of the wafer being aligned by the use of the alignment markers passing through the wafer.
The layer provided on the surface of the wafer may be an oxide (or may be a nitride) which may be provided by Plasma Enhance Chemical Vapour Deposition (PECVD). Of course, the skilled person will realise that by the use of known micro-machining techniques many other layers could be provided. Further, the layers could be provided by many deposition techniques other than PECVD. A polyimide or photoresist may also be used.
According to a fifth aspect of the invention there is provided a method of separating portions of at least two wafers comprising the following steps:
a) providing two wafers separated by an insulating layer wherein the insulating layer is fabricated from at least two sub layers of material having different etching rates;
b) etching the insulating layer to remove portions of that insulating layer wherein the time of the etch is controlled to ensure that at least one sub layer is substantially completely removed within the portion being etched and at least one other sub layer is partially left un-etched in the portion being removed.
This method is advantageous in that it can reduce problems encountered with stiction between the two wafers which can arise during removal of the insulating layer.
The portion of the sub layer which is left un-etched may be arranged to have a small cross sectional area when compared to the area covered by the portion of the insulating layer being removed. Perhaps the un-etched portion is less than substantially 10%, perhaps less than substantially 5% of the portion being etched. As the skilled person will appreciate stiction is a function of the cross sectional area and therefore if the area is significantly reduced then the amount of stiction experienced between the two wafers will also be significantly reduced.
According to a sixth aspect of the invention there is provided a method of separating a first portion of material from a second portion of material comprising using a dry etching process to etch between the portions and subsequently using a dry agent to clean any residues remaining from the etch.
The first portion and the second portion may be the same material or they may be different materials. Indeed, the dry etch may be used to etch a material which is different from both of the first portion and the second portion. Indeed, such a process may be used to etch an insulating layer from between two wafers as described herein.
Prior art techniques of separating portions of two adjacent portions have encountered problems where the portions stick to one another due to stiction and surface tension caused by liquids left between the two portions by the fabricating processes. Clearly, by using a dry agent there will be no liquid between the portions and therefore the stiction and surface tension problems should be overcome.
The dry process may use HF gas. Plasma etching techniques may also be employed should the selectivity of the etch between the first and second portions and the material being etched be sufficiently high. If the method is applied to the silicon on insulator technology according to the first aspect of the invention there would need to be a sufficiently high selectivity between the silicon and the insulator. If the selectivity is not high enough the silicon may also be etched reducing the performance of any device fabricated from the wafers.
Preferably the dry cleaning agent is steam but any other suitable agent to remove the residues may be used. The steam may be super-heated. Of course, the dry agent may be the gaseous/vapour phase of any liquid and may be thought of as an agent wherein there is never any liquid present.
Preferably the portions of material are held at a temperature above the boiling point of the agent to be used. This ensures that as the agent is used to clean the wafers no drops of the liquid phase condense or are left on the portions of material.
According to a seventh aspect of the invention there is provided a micro-mechanical ring gyroscope having a ring element which is fabricated from a material having anisotropic properties, the dimensions of at least a portion of the element being thicker or thinner when compared to the remainder of the element so that the gyroscope functions as if it were manufactured from a material having isotropic properties.
This has the advantage that material showing imperfect properties can be used to fabricate the gyroscope and yet the gyroscope will still function accurately. Such gyroscopes have a number of applications including: vehicle control, smart munitions, robotics, virtual reality and medicine.
Preferably the gyroscope is fabricated from silicon with the lattice spacing of substantially  less than 100 greater than  as the plane of the silicon wafer. It is known that within  less than 100 greater than  silicon the modulus of rigidity and the radial Young""s modulus vary significantly in a cos 4xcex8 manner (where xcex8 is an angle within a plane in the silicon from a reference point on that plane).
Previously micro-mechanical gyroscopes have been fabricated from silicon wafers with substantially  less than 111 greater than  as the plane of the wafer. In such  less than 111 greater than  oriented silicon the radial Young""s modulus varies little with angular orientation. As the skilled person will appreciate  less than 111 greater than  silicon is much more expensive than  less than 100 greater than  silicon and it is therefore advantageous to be able to use  less than 100 greater than  silicon. However, until the realisation of this invention it was not possible to use  less than 100 greater than  silicon without employing tuning methods (for example laser trimming) because the anisotropic nature of the material led to inaccurate performance of the gyroscope. Using  less than 100 greater than  silicon materials may also make integration of on chip electronics simpler.
Preferably the gyroscope has a number of sensing elements. The sensing elements may be equispaced around a circle. There may be eight sensing elements. Alternatively there may be 16, 32, 64 or 128 sensing elements.
The gyroscope may be fabricated from a ring supported by suspension elements/ligaments with at least eight sensing elements which may be arranged at 45xc2x0 intervals around a circle. If such a gyroscope (having drive and sense modes) were fabricated from  less than 100 greater than  silicon with all of the sensing elements of equal dimensions the effect of the anisotropy would be to cause a split in the frequencies of the drive and sense modes. This split is significant and causes a reduction in gyroscope sensitivity as the modes do not efficiently couple under an applied rate of turn and high levels of mechanical coupling swamp the sense signal. It may be desired to thicken a sensing element substnatially in the range 0.1 xcexcm to 50 xcexcm when compared to the unthickened sensing element.
One embodiment of this would be to thicken portions of the ring associated with alternative sensing elements when compared to the remaining portions of the ring (as if in a cos 4xcex8).
Although the required thickening of the elements will vary according to the dimensions of the wafer and size of device. For a 100 xcexcm thick ring the portion of increased thickness may be thickened when compared to the remaining portions of the ring by substantially 13 xcexcm. However, this thickening is merely an indication since the precise increase needs to be calculated for each particular design. Other stages may be thickened to account for anisotropy in  less than 100 greater than  silicon. It may be desired to thicken a sensing element substnatially in the range 0.1 xcexcm to 50 xcexcm when compared to the unthickened sensing element.
According to an eighth aspect of the invention there is provided a method of fabricating a micro-mechanical ring gyroscope according to the seventh aspect of the invention which uses the method of the first aspect of the invention.
Fabricating a gyroscope according to this method is advantageous in that the process is CMOS compatible allowing integrated packages (including both the sensor and the electronics) or indeed fully integrated devices to be fabricated.
The method may comprise providing substantially all of the necessary sensors and processing electronics in a single package or may comprise providing a sensor in a first package and substantially all of the required processing circuitry in a second or multiple packages.
The skilled person will appreciate that the gyroscope is a micro-mechanical sensor.
The method may comprise determining the degree of misalignment of the crystal lattice before fabricating the gyroscope. For example X-ray photo spectroscopy (XPS) may be used. Further, once the degree of misalignment has been calculated the method may comprise calculating the degree of change required in the thickness dimension to compensate for the misalignment of the crystal lattice.
The method may comprise the step of etching an alignment marker using an etch having anisotropic properties dependent upon crystal planes into the wafer prior to fabrication of the gyroscope in order to determine the orientation of the crystal planes. The etch may be a wet etch.
The method may also comprise calculating the necessary alterations to the dimensions of the gyroscope in order to allow for the mis-alignment of the crystal planes from the optimum orientation. Alternatively, or additionally, a mask used to fabricate the gyroscope may be aligned with the alignment markers fabricated on to the wafer by the anisotropic etch rather than with the wafer flats. In yet another embodiment once the degree of misalignment has been determined the misalignment could be allowed for in the completed gyroscope. For instance the gyroscope may be trimmed, or may be actively tuned.
According to a ninth aspect of the invention there is provided a micro-inertial mechanical sensor having at least one element which is fabricated from a material having anisotropic properties, the dimensions of the element having the thickness dimension designed so that the sensor functions as if it were manufactured from a material having isotropic properties.
The micro-inertial sensor may be a gyroscope.